QoS based dynamic execution engine selection
US9495161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask. The processor includes an arbitration unit that determines instruction priority among each instruction, assigns an instruction for each available core, and signals the instruction store.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.