Error framework for a microprocesor and system
US9495233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2011 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing an error framework for a microprocessor and for a system having such a microprocessor. The error framework may alternatively be implemented by a hardware component, such as a peripheral device for integration into a system. In one embodiment, an error framework of a microprocessor or a hardware component includes an error detection unit to capture an error within the hardware component; a state detection unit to capture error context information when the error is detected within the hardware component; an error event definition unit to define a unique error event representing a combination of the error and the error context information; and a configuration unit to define an error event response based on the unique error event. The error context information may include, for example, a known state of a system at the time the error occurs or a known state of the hardware component or microprocessor within which the error is detected at the time the error occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.