Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)
US9495285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Mar 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.