Data processing device utilizing way selection of set associative cache memory based on select data such as parity data
US9495299B2 · kind B2 · utility
3Cited by
2References
16Claims
0Family size
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Key dates
| Filing date | Dec 26, 2011 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jul 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Part of a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read. Further, when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data. For select data used for selecting a way, e.g. parity data in connection with tag address information is used. A way to read a cache tag from is selected based on a value of parity data and further, the way of a cache entry to perform cache fill on is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.