Dynamic management of a processor state with transient cache memory
US9495306B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jan 29, 2016 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jan 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to some embodiments, a method for controlling a processor state with transient cache memory is described. The method may include identifying, via a processor, a memory section having a memory address, retrieving, via the processor, memory control information, and controlling the processor state by allowing a memory access to the transient cache memory based on the memory control information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.