Shift register, driver circuit and display device
US9495929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.