Noise mitigation for write precompensation tuning
US9495987B1 · kind B1 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | May 1, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | May 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2508
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology provides techniques for mitigating write-to-write bit error rate fluctuations that decrease accuracy of write precompensation (WPC) tuning. According to one implementation, such write-to-write bit error rate fluctuations are mitigated if a predetermined pattern is written at a particular radial offset from a target data track prior to testing a WPC register in association with the target data track. Selection of the particular radial offset can be performed according to an iterative offset track clean-up disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.