Memory cell and memory device having the same
US9496016B2 · kind B2 · utility
3Cited by
21References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.