Compound semiconductor device comprising compound semiconductor layered structure having buffer layer and method of manufacturing the same
US9496380B2 · kind B2 · utility
1Cited by
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15Claims
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Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Mar 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.