Multiphase clock data recovery for a 3-phase interface
US9496879B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2015 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.