Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support
US9500706B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Nov 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.