External memory tagging and stack ordering of memory tags
US9501412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Apr 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.