System and method for assertion publication and re-use
US9501598B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jan 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools. Another designer may re-use the assertion by searching for and selecting a relevant published assertion, instantiating and binding the selected assertion to specific elements of a second circuit design, and verify the assertion for the second circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.