Modular cell for a memory array, the modular cell including a memory circuit and a read circuit
US9502110B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.