Semiconductor device
US9502133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell (101) includes a memory transistor (10A) having channel length L1 and channel width W1, and a plurality of select transistors (10B) each electrically being connected in series with the memory transistor and independently having channel length L2 and channel width W2, wherein each of the memory transistor and the plurality of select transistors includes an active layer (7A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L2 is greater than channel length L1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.