Nonvolatile semiconductor memory device and method of manufacturing the same
US9502431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jun 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.