Deskew of rising and falling signal edges
US9503065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.