Integrated circuit having multiple identified identical blocks
US9503089B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i≠N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first output 1 of the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.