Digital signal processing for PLC communications having communication frequencies
US9503157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2014 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/121
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (ADC), and an analog input signal from power distribution lines that carry power using alternating current (AC) to a digital form. This input digital signal can be an oversampled digital signal, where the digital signal is oversampled relative to downstream processing (e.g., FFT-based processing). A processing circuit(s) can then be used to decimate the input digital signal according to a decimation rate. A reference signal can be generated by the processing circuit that is responsive to the decimation rate. The processing circuit can also be used to detect a change in a phase difference between the AC and reference signal and to modify, in response to detecting a change in the phase difference, the decimation rate to counteract the detected change in the phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.