Integrated circuit testing architecture
US9506980B2 · kind B2 · utility
0Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | May 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2844
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In accordance with one aspect of the present description, an interface between an integrated circuit device and a test controller for testing the integrated circuit device includes a plurality of boards coupled together. In one embodiment, the test interface includes a plurality of interchangeable auxiliary boards, each having test circuitry, which may be coupled to a primary board and reused as appropriate to test various integrated circuits. Other aspects are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.