Patent · US Active

Integrated circuit with distributed clock tampering detectors

US9506981B2 · kind B2 · utility

0Cited by
4References
9Claims
0Family size

Assignee

Inventor

Key dates

Filing dateAug 3, 2015
Grant dateNov 29, 2016
Priority date—
Expiry dateAug 3, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K19/003
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.