System and method for managing power in a chip multiprocessor using a proportional feedback mechanism
US9507405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Dec 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.