Transition rate controlled bus driver circuit with reduced load sensitivity
US9507409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2013 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.