Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources
US9507596B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Nov 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.