Circuit arrangement for modeling transistor layout characteristics

US9507897B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yi Wang · Chengdu, CN
• Chia-Ying Lin · Ann Arbor, US
• Run Gao · Beijing, CN
• Hung-Han Lin · Hsinchu, TW
• Chia-Chi Ho · Xihu, TW
• Chung-Shi Chiang · 埔鹽鄉, TW

Key dates

• Filing date: Aug 12, 2014
• Grant date: Nov 29, 2016
• Expiry date: Sep 12, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D99/00
• WIPO field: Control
• WIPO sector: Instruments

Abstract

One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device.