Hardware-amenable connected components labeling
US9508003B2 · kind B2 · utility
5Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Apr 15, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Apr 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2013/0081
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The subject disclosure is directed towards performing connected components in hardware, such as an FPGA, which is facilitated by a linked list structure that does not grow. During a connected components graph labeling process, when a merge is encountered, the data structure comprising labels and associated equivalency data swaps the equivalency data of the two vertices whose different labels produced the merge condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.