Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
US9508704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Feb 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.