Semiconductor device and method of fabricating the same
US9508737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.