Thin film transistor substrate and method for manufacturing the same
US9508750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2014 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate wiring, a source electrode, a source-electrode connecting wiring, a pixel electrode, a gate-terminal extraction electrode, and a source-terminal extraction electrode are formed in the same layer on a planarization insulating film. The gate wiring is connected to a gate electrode through a gate-electrode-portion contact hole. The source electrode is connected to a semiconductor film through a source-electrode-portion contact hole. The source-electrode connecting wiring is connected to the semiconductor film and a source wiring through the source-electrode-portion contact hole and a source-wiring-portion contact hole, respectively. The pixel electrode is connected to the semiconductor film through a drain (pixel)-electrode-portion contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.