Array substrate, method of manufacturing array substrate and display device
US9508762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K99/00
Abstract
Embodiments of the present invention disclose an array substrate, a method of manufacturing an array substrate and a display device, which belong to field of display technology. The method includes: forming a gate metal pattern and a gate insulating layer in turn on a base substrate; forming a source-drain metal pattern that is made of a preset metal on the base substrate, on which the gate insulating layer is formed, the source-drain metal pattern comprising a source electrode and a drain electrode and the preset metal including at least copper; forming a silicon nitride layer and a silicon oxide layer in turn on the base substrate, which compose a passivation layer; forming a trench in the passivation layer at a position corresponding to a gap between the source electrode and the drain electrode, wherein a width of the trench in the silicon oxide layer is smaller than a width of the trench in the silicon nitride layer and is larger than or equal to a distance of the gap between the source electrode and the drain electrode; forming an oxide trench pattern on the source-drain metal pattern, with is not in contact with the silicon nitride layer. The present invention solves problems…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.