Transistors, methods of manufacturing the same, and electronic devices including transistors
US9508865B2 · kind B2 · utility
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2References
24Claims
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Key dates
| Filing date | Mar 20, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
According to example embodiments, a transistor includes a gate, a channel layer that is separate from the gate, a gate insulating layer between the gate and the channel layer, and a source electrode and a drain electrode respectively contacting a first region and a second region of the channel layer. The gate insulating layer includes an impurity metal containing region that includes an impurity metal and contacts the channel layer. The gate insulating layer includes an impurity metal non-containing region contacting the gate that is not doped with the impurity metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.