Simultaneous accommodation of a low power signal and an interfering signal in a radio frequency (RF) receiver
US9509351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Mar 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/28
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.