Codec inversion detection
US9510309B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 2015 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | May 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W76/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes a receiver and a processor. The receiver is configured to receive a signal. The processor is configured to generate a first flag indicating whether the signal satisfies one or more first conditions that are based on a number of detected correlation peaks associated with the signal, a correlation peak amplitude, or both, and to generate a second flag indicating whether an inverted signal satisfies one or more second conditions. The processor is further configured to generate a first value of a first synchronization sign indicator associated with the signal and to generate a second value of a second synchronization sign indicator associated with the inverted signal. The processor is also configured to generate an invert flag that indicates whether synchronization inversion is detected in the signal based at least in part on the first flag, the second flag, the first value, and the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.