Semiconductor device having stacked layers
US9514792B2 · kind B2 · utility
37Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes a second transistor. The second substrate is stacked with the first substrate such that the sense amplifier amplifies data transferred through the bit line from a selected one of the memory cells. The first transistor is lower in carrier mobility than the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.