Volatile memory self-defresh
US9514802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (TRP) and/or a row active time (TRAS) for each of the plurality of rows to clean the data from the memory cell array. Memory data can be cleaned from the memory cell array responsive to the violations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.