Nonvolatile memory device, erase method thereof and memory system including the same
US9514828B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and string select transistors between the memory cells and a bit line. The erase method includes applying a precharge voltage during a first time to a first string select line, floating the first string select line during a second time after the first time, and applying an erase voltage to the substrate after the first time. The first string select line is connected to the string select transistors at a first height in the cell strings of a same row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.