Semiconductor device and method of manufacturing the same
US9515082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.