Semiconductor device, electronic device, and method of fabricating the same
US9515086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.