Socket structure for three-dimensional memory
US9515125B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2015 |
| Grant date | Dec 6, 2016 |
| Priority date | — |
| Expiry date | Apr 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.