Dynamically improving performance of a host memory controller and a memory device
US9519428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2012 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jan 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, systems, and computer-readable media for dynamically improving performance of a host memory controller and a hosted memory device are presented. According to one or more aspects, a memory controller may establish a data connection with a memory device. The memory controller may perform a first write operation of a plurality of write operations to the memory device using a first block size. Subsequently, the memory controller may perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size. The memory controller then may determine an optimal value for a block size parameter based at least in part on the plurality of write operations. Thereafter, the memory controller may use the optimal value for the block size parameter in performing one or more regular tasks involving the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.