Optimized fused-multiply-add method and system
US9519458B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical additions in parallel paths. The fused-multiply-add system also includes at least one leading zero counter for counting a number of leading zero bits provided by at least one of the adder and the subtractor to provide at least one normalization shift amount. Finally, the fused-multiply-add system includes a multiplexer coupled to the adder and the subtractor for providing an appropriate output based upon a sign bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.