Handling system interrupts with long-running recovery actions
US9519532B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Jan 20, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.