Serial bus buffer with noise reduction
US9519612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Feb 23, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.