Processor with instruction variable data distribution
US9519617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2012 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jul 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.