Pipeline dependency resolution
US9519944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to dependency resolution among processor pipelines. In one embodiment, an apparatus includes a first special-purpose pipeline configured to execute, in parallel, a first type of graphics instruction for a group of graphics elements and a second special-purpose pipeline configured to execute, in parallel, a second type of graphics instruction for the group of graphics elements. In this embodiment, the apparatus is configured, in response to dispatch of an instruction of the second type, to mark a particular instruction of the first type with information indicative of the dispatched instruction. In this embodiment, the particular instruction and the dispatched instruction correspond to the same group of graphics elements. In this embodiment, the apparatus is configured to stall performance of the dispatched instruction until the first special-purpose pipeline has completed execution of the marked particular instruction. Exemplary instruction types include interpolate and sample instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.