Resistive memory write operation with merged reset
US9520192B2 · kind B2 · utility
31Cited by
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20Claims
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Key dates
| Filing date | Jun 30, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Aug 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.