Circuit with reduced noise and controlled frequency
US9520356B1 · kind B1 · utility
11Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Sep 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A die is packaged by flip-chip mounting the die with the active side facing a low loss substrate. A ground plane is coupled to the active side of the die by vias through the low loss substrate. The ground plane is positioned to concentrate high frequency electromagnetic fields in the low loss substrate. A tuning height can be adjusted to tune the center frequency of a circuit in the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.