Thin film transistor array substrate and method for manufacturing the same
US9520414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Jul 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.