Delay structure for a memory interface
US9520864B2 · kind B2 · utility
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6References
24Claims
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Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Oct 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.