Digital phase locked loop (PLL) system with frequency band jump in lock mode
US9520885B1 · kind B1 · utility
3Cited by
12References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 3, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Dec 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) control system is provided that includes a digital controlled oscillator (DCO). The DCO comprises a delay cell chain comprising a number (B) of delay cells, and a load control cell comprising a number (L) of load cells. A system also includes that module that is configured to dynamically adjust the number (B) of delay cells that are activated and part of the delay cell chain and the number (L) of load cells that are switched on, when the PLL control system is operating in a lock mode, to control an amount of delay in the DCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.